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Simulation of slow current transients and current collapse in GaN FETs
Authors:H Takayanagi  H Nakano  K Yonemoto  K Horio
Affiliation:(1) Faculty of Systems Engineering, Shibaura Institute of Technology, 307 Fukasaku, Minuma-ku, Saitama 337-8570, Japan
Abstract:Two-dimensional transient simulations of GaN MESFETs are performed in which a three-level compensation model is adopted for a semi-insulating buffer layer, where a shallow donor, a deep donor and a deep acceptor are considered. When the drain voltage V D is raised abruptly (while keeping the gate voltage V G constant), the drain current I D overshoots the steady-state value, and when V D is lowered abruptly, I D remains a low value for some periods, showing drain-lag behavior. These are explained by the deep donor’s electron capturing and electron emission processes. We also calculate a case when both V D and V G are changed abruptly from an off point, and quasi-pulsed I-V curves are derived from the transient characteristics. It is shown that the drain currents in the pulsed I-V curves are rather lower than those in the steady state, indicating that so-called current collapse could occur due to deep levels in the semi-insulating buffer layer. It is also shown that the current collapse is more pronounced when V D is lowered from a higher voltage during turn-on, because the trapping effects become more significant.
Keywords:GaN FET  Current collapse  Deep level  Drain lag
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