| 应用虚拟仪器(VI)技术开发集成电电路闩锁测试系统 |
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| 引用本文： | 钟征宇.应用虚拟仪器(VI)技术开发集成电电路闩锁测试系统[J].电子质量,2003(8):J013-J015. |
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| 作者姓名： | 钟征宇 |
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| 作者单位： | 中国赛宝实验室可靠性研究分析中心,广州,510610 |
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| 摘 要： | 闩锁(latch-up)效应严重影响了CMOS集成电路的可靠性,如何对其进行快速有效地测试是很有必要的,本文主要介绍了代表了当今世界测试仪器技术发展方向的虚拟仪器技术(VI)及其在开发集成电路闩锁测试系统过程中的应用.
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| 关 键 词： | 虚拟仪器 闩锁效应 CMOS集成电路 测试 |
Development of the IC latch-up test system with technology of Virtual Instrument(Ⅵ) |
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| ZHONG Zheng-yu The Reliability Research & Analysis Center of China Ceprei Laboratory,Guangzhou.Development of the IC latch-up test system with technology of Virtual Instrument(Ⅵ)[J].Electronics Quality,2003(8):J013-J015. |
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| Authors: | ZHONG Zheng-yu The Reliability Research & Analysis Center of China Ceprei Laboratory Guangzhou |
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| Affiliation: | ZHONG Zheng-yu The Reliability Research & Analysis Center of China Ceprei Laboratory,Guangzhou,510610 |
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| Abstract: | In this paper we present an automated,high speed relay-based latch-up test system which is developed with the leading-edge technology of Virtual Instrument(VI). |
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| Keywords: | Virtual instrument latch-up test |
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