| 纳米集成电路静态功耗机理及低功耗设计技术 |
| |
| 引用本文： | 徐懿,李丽,高明伦,黄壮雄,杨盛光. 纳米集成电路静态功耗机理及低功耗设计技术[J]. 微电子学与计算机, 2007, 24(5): 184-188,192 |
| |
| 作者姓名： | 徐懿 李丽 高明伦 黄壮雄 杨盛光 |
| |
| 作者单位： | 南京大学,物理系微电子设计研究所,江苏,南京,210093;南京大学,江苏省光电信息功能材料重点实验室,江苏,南京,210093 |
| |
| 基金项目： | 国家自然科学基金;江苏省高技术研究发展计划项目 |
| |
| 摘 要： | 对当前纳米级低功耗设计中静态功耗的产生机理以及各种降低漏电流功耗的电路设计理论及其特点做详细的论述．以期为相关研究：设计人员提供有益参考。
|
| 关 键 词： | 低功耗设计 阈值电压 堆垛效应 |
| 文章编号： | 1000-7180（2007）05-0184-05 |
| 修稿时间： | 2006-04-29 |
Static Power Mechanism and Low-Power Design Techniques in Nanometer CMOS Circuits |
| |
| XU Yi,LI Li,GAO Ming-lun,HUANG Zhuangxiong,YANG Sheng-guang. Static Power Mechanism and Low-Power Design Techniques in Nanometer CMOS Circuits[J]. Microelectronics & Computer, 2007, 24(5): 184-188,192 |
| |
| Authors: | XU Yi LI Li GAO Ming-lun HUANG Zhuangxiong YANG Sheng-guang |
| |
| Affiliation: | 1. Institute of VLSI Design, Physics Department, Nanjing University, Nanjing 210093, China; 2 Key Laboratory of Advanved Potoelectricity Material of Jiangsu Provice, Nanjing University, Nanjing 210093, China |
| |
| Abstract: | Due to the popularity of portable electronic system, Power is becoming more and more important in nanometer CMOS circuits as well as area and speed for designing VLSI. The source of power consumption is changing evidently in nanometer CMOS circuits. The leakage current is going to be the main contributor to power dissipation. All leakage mechanisms contributing to the off-state current are explored and different circuit techniques to reduce the leakage power are discussed in this paper in order to provide some valuable reference for related research and design work. |
| |
| Keywords: | low-power threshold voltage stacking effect |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
|
