基于CMOS工艺平台反熔丝FPGA实现

由于反熔丝FPGA具有低功耗、高密度、可靠性高、抗辐射能力强以及设计上具有灵活性等优势,在军事和卫星领域得到广泛的应用。但由于工艺的限制,目前国内未见相关研究的报道。根据目前现状,利用现有的工艺,开发出一种可以与普通CMOS工艺兼容的反熔丝单元。经过测试,其熔断后的电阻约为330~400,同时给出了基于此种反熔丝单元的阵列设计,体现了低功耗、高密度、易实现等优势。此设计不但满足了目前的工作需要,并为以后反熔丝电路的设计提供了有用的参考,为航天和军事领域的应用提供了有力的支持和保障。

The Antifuse FPGA Based on CMOS Process

The antifuse FPGA is widely used in the field of military affairs and satellite, because its low power, high density and dependability, better in radiation hardness, flexible in designs. But the process was limited in our country, we have not found the researches about this technique. So the tectonic of we hold is used to develop a new antifuse cell, which is compatible to CMOS process. The cell＇s resistance after fusion is 330Ω-400Ω, and design of array has been given. The advantages of low power, high density and flexible in designs are embodied. The design not only satisfied the needs of present work, but supplies a worthful reference for antifuse circuit design in future, it will provide good supports in the aerospace and military applications.