| 一种高速开关电容动态锁存比较器分析与设计 |
| |
| 引用本文： | 范晓捷,黄峰,魏斌,李静,张凯虹. 一种高速开关电容动态锁存比较器分析与设计[J]. 电子与封装, 2012, 12(6): 12-15 |
| |
| 作者姓名： | 范晓捷 黄峰 魏斌 李静 张凯虹 |
| |
| 作者单位： | 1. 中国电子科技集团公司第58研究所,江苏无锡,214035
2. 黄山旅游发展股份有限公司云谷索道分公司,安徽黄山,242709 |
| |
| 摘 要： | 设计了一种基于CMOS工艺的开关电容动态锁存比较器。该比较器包含一个共模不敏感全差分开关电容采样级和一级动态锁存比较器。开关电容采样级验证了比较器的输入共模范围,动态锁存器采用两个正反馈锁存器和额外的反馈环路提高了锁存的速度。基于0.18μm 1.8V CMOS工艺进行了版图设计和后仿真,结果表明该比较器可以应用于200 MSPS高精度流水线模数转换器。
|
| 关 键 词： | 高速高精度模数转换器 比较器 正反馈 锁存器 |
Analysis and Design of a High Speed Switched Capacitor Dynamic Comparator |
| |
| FAN Xiao-jie,HUANG Feng,WEI Bin,LI Jing,Zhang Kai-hong. Analysis and Design of a High Speed Switched Capacitor Dynamic Comparator[J]. Electronics & Packaging, 2012, 12(6): 12-15 |
| |
| Authors: | FAN Xiao-jie HUANG Feng WEI Bin LI Jing Zhang Kai-hong |
| |
| Affiliation: | 1.China Electronic Technology Group Corporation No.58 Research Institute ,Wuxi 214035,China; 2. Huangshan Tourism Development Co. Ltd, Huangshan 242709, China) |
| |
| Abstract: | A high speed switched capacitor dynamic comparator circuit in CMOS technology is presented. The comparator includes a switched capacitor sampling stage and a dynamic latched comparator.The input voltage range is improved by applying a switched capacitor sampling stage in the input stage.The speed of the dynamic latch is improved by employing two cross-coupled latch and other feedback circuits.The comparator is designed and simulated in a 0.18 la m 1.8V CMOS technology and the result shows that it meets the requirement of a 200 MSPS high resolution pipelined ADC. |
| |
| Keywords: | high speed high resolution ADC comparator positive feedback latch |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
|
