Design of a hardware arbiter for multi-microprocessor systems

A simple cost-effective hardware arbiter suitable for multi-microprocessor systems is described. The number of processors is not limited and any one can acquire mastership of the common bus on a priority basis. A daisychain configuration is used to minimize the required interconnection between processor modules and priority is allocated on a round-robin basis. In the realization described, the current bus master is given lowest priority so that it cannot ‘hog’ the bus by making repeated requests.Typical queueing performance of the system is described and metastability problems in flipflop-based arbiters are discussed.