| 亚65nm工艺新型p结构多米诺与门设计 |
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| 引用本文： | 汪金辉,宫娜,冯守博,段丽莹,侯立刚,吴武臣,董利民.亚65nm工艺新型p结构多米诺与门设计[J].半导体学报,2007,28(11):1818-1823. |
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| 作者姓名： | 汪金辉 宫娜 冯守博 段丽莹 侯立刚 吴武臣 董利民 |
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| 作者单位： | 北京工业大学集成电路与系统研究室，北京 100022;河北大学电子信息工程学院，保定 071002;北京工业大学集成电路与系统研究室，北京 100022;北京工业大学集成电路与系统研究室，北京 100022;北京工业大学集成电路与系统研究室，北京 100022;北京工业大学集成电路与系统研究室，北京 100022;北京工业大学集成电路与系统研究室，北京 100022 |
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| 摘 要： | 利用休眠晶体管、多阈值和SEFG技术(源跟随求值门技术),设计了一种新型的p结构多米诺与门.HSPICE仿真结果表明,在相同的时间延迟下,与标准双阈值多米诺与门、标准低阈值多米诺与门和SEFG结构相比,提出的新型多米诺与门的漏电流分别减小了43%,62%和67%,噪声容限分别增大了3.4%,23.6%和13.7%.从而有效地解决了亚65nm工艺下多米诺与门存在的漏电流过大,易受干扰的问题.分析并得到了不同结构的休眠多米诺与门的漏电流最低的输入矢量和时钟状态.
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| 关 键 词： | 低功耗 漏电流 p型多米诺与门 噪声容限 工艺 结构 多米诺 设计 Technologies CMOS Design Gate Domino 状态 时钟 矢量 输入 休眠晶体管 分析 问题 干扰 存在 噪声容限 漏电流 |
| 文章编号： | 0253-4177（2007）11-1818-06 |
| 收稿时间： | 5/7/2007 12:22:42 PM |
| 修稿时间： | 6/1/2007 10:20:25 AM |
A Novel p-Type Domino AND Gate Design for Sub-65nm CMOS Technologies |
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| Wang Jinhui,Gong N,Feng Shoubo,Duan Liying,Hou Ligang,Wu Wuchen and Dong Limin.A Novel p-Type Domino AND Gate Design for Sub-65nm CMOS Technologies[J].Chinese Journal of Semiconductors,2007,28(11):1818-1823. |
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| Authors: | Wang Jinhui Gong N Feng Shoubo Duan Liying Hou Ligang Wu Wuchen and Dong Limin |
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| Affiliation: | VLSI and System Laboratory,Beijing University of Technology,Beijing 100022,China;College of Electronic and Informational Engineering,Hebei University, Baoding 071002,China;VLSI and System Laboratory,Beijing University of Technology,Beijing 100022,China;VLSI and System Laboratory,Beijing University of Technology,Beijing 100022,China;VLSI and System Laboratory,Beijing University of Technology,Beijing 100022,China;VLSI and System Laboratory,Beijing University of Technology,Beijing 100022,China;VLSI and System Laboratory,Beijing University of Technology,Beijing 100022,China |
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| Abstract: | A novel p-type Domino AND gate utilizing the sleep transistor,dual threshold voltage,and source following evaluation gate (SEPG) techniques is proposed.HSPICE simulation results prove that the leakage current of the proposed design can be reduced by 43%,62%,and 67% while improving the noise margin 3.4%,23.6%,and 13.7% when compared to standard dual Vt Dominos,standard low Vt dominos,and the SEFG structure under similar delay time,respectively.Therefore,the proposed Dominos AND gate solves the high leakage current and deteriorated robustness problem in sub-65nm CMOS technologies.Finally,the inputs and clock signals combination sleep state dependent on leakage current characteristics is analyzed,and the optimal sleep state is obtained. |
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| Keywords: | low power leakage current p-type Dominos AND gate noise immunity |
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