| 基于AVS的变字长解码器的设计及其FPGA验证 |
| |
| 引用本文： | 李晓燕,张卫宁,袁鲲,赵建全. 基于AVS的变字长解码器的设计及其FPGA验证[J]. 电子技术应用, 2009, 35(1) |
| |
| 作者姓名： | 李晓燕 张卫宁 袁鲲 赵建全 |
| |
| 作者单位： | 山东大学,信息科学与工程学院,山东,济南,250100;山东大学,信息科学与工程学院,山东,济南,250100;山东大学,信息科学与工程学院,山东,济南,250100;山东大学,信息科学与工程学院,山东,济南,250100 |
| |
| 摘 要： | 提出了一个完整的AVS变字长解码器的硬件架构,在设计中采用加入FIFO的方法构成流水结构,并尽量减少变字长解码器中各子模块的运行节拍,大大提高了系统的运行速度。本设计已经通了FPGA验证。该变字长解码器不仅可以成为其他AVS解码器的硬件加速器,同时由于视频编解码标准的相似性,稍加改动即可应用在其他的视频标准中。
|
| 关 键 词： | AVS 变字长解码器 FPGA |
Design of variable length decoder for AVS and it's implementation on FPGA |
| |
| LI Xiao Yan,ZHANG Wei Ning,YUAN Kun,ZHAO Jian Quan. Design of variable length decoder for AVS and it's implementation on FPGA[J]. Application of Electronic Technique, 2009, 35(1) |
| |
| Authors: | LI Xiao Yan ZHANG Wei Ning YUAN Kun ZHAO Jian Quan |
| |
| Affiliation: | LI Xiao Yan,ZHANG Wei Ning,YUAN Kun,ZHAO Jian Quan (School of Information Science and Engineering,Shandong University,Jinan 250100,China) |
| |
| Abstract: | This paper proposes an entire VLD hardware architecture for AVS. It uses FIFO to make the pipeline architecture, and reduces the runtime of each submodule of VLD, so it obviously improves the working speed of the entire system. This design has been verified by FPGA.This VLD not only can be used as an accelerator for other AVS decoders but also can be used in other video standard with a little changed because of the comparability of all the video standards. |
| |
| Keywords: | AVS FPGA |
| 本文献已被 CNKI 万方数据 等数据库收录！ |
|
