On state reduction of incompletely specified finite state machines

State reduction of incompletely specified finite state machines (ISFSMs) is an important task in optimization of sequential circuit design and known as an NP-complete problem. Removal of redundant states reduces the logic, because of this, chip area decreases. In addition, test generation is easier when the sequential circuit is irredundant. In this paper, we present a heuristic for state reduction of ISFSMs. The proposed heuristic is based on a branch-and-bound search technique and identification of sets of compatible states of a given ISFSM specification. We have obtained results as good as the best exact method in the literature but with significantly better run-times.