| 宽带低相噪频率综合器设计与实现 |
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| 引用本文： | 李昂,于萌,朱康生. 宽带低相噪频率综合器设计与实现[J]. 电子科技, 2015, 28(7): 54 |
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| 作者姓名： | 李昂 于萌 朱康生 |
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| 作者单位： | (西安电子工程研究所 专业3部,陕西 西安 710100) |
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| 摘 要： | 为满足某雷达信号设计要求,文中基于国产小数锁相环芯片GM4704产生7.12～9.12 GHz的信号,采用传统的PLL方式产生,低相位噪声、低杂散的频率综合器。同时,给出了设计过程并对相关的设计参数进行分析,应用相关的PLL仿真软件对环路滤波器进行仿真设计,通过实际电路测试,相位噪声达到-97 dBc/Hz@1 kHz与理论计算较接近,杂散达到-70 dB。
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| 关 键 词： | 频率合成器 宽带 低相噪 PLL GM4704 |
Design and Implementation of Wide-band Low Phase Noise Frequency Synthesizers |
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| LI Ang,YU Meng,ZHU Kangsheng. Design and Implementation of Wide-band Low Phase Noise Frequency Synthesizers[J]. Electronic Science and Technology, 2015, 28(7): 54 |
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| Authors: | LI Ang YU Meng ZHU Kangsheng |
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| Affiliation: | (Specialized Unit 3,Xi'an Electronic Engineering Research Institute,Xi'an 710100,China) |
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| Abstract: | In order to meet the design requirement of the radar signal,this article describe a frequency synthesizer based on the decimal phase locked loop chip GM4704 made in China.The conventional PLL technique is adopted to generate low phase noise signal from 7.12 to 9.12 GHz.The design process and the related design parameters are given.Also we use the PLL simulation to design the loop band filter.Circuit tests show that the phase noise can reach to -97 dBc/Hz@1 kHz,which is close to the theoretical value;the spurious can reach -71 dB. |
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| Keywords: | wide-band low phase noise PLL GM4704, |
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