| TRANSIENT CHARACTERISTIC ANALYSIS OF HIGH TEMPERATURE CMOS DIGITAL INTEGRATED CIRCUITS |
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| 引用本文： | 柯导明,冯耀兰,童勤义,柯晓黎. TRANSIENT CHARACTERISTIC ANALYSIS OF HIGH TEMPERATURE CMOS DIGITAL INTEGRATED CIRCUITS[J]. 电子科学学刊(英文版), 1994, 11(2): 104-115. DOI: 10.1007/BF02778359 |
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| 作者姓名： | 柯导明 冯耀兰 童勤义 柯晓黎 |
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| 作者单位： | Microelectronics Center Southeast University，Nanjing 210018，Microelectronics Center Southeast University，Nanjing 210018，Microelectronics Center Southeast University，Nanjing 210018，The Planning Committee of Hefei City，Hefei 230061 |
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| 基金项目： | Supported by the National Native Science Foundation of China |
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| 摘 要： | This paper analyses the transient characteristics of high temperature CMOS inverters and gate circuits, and gives the computational formulas of their rise time, fall time and delay time. It may be concluded that the transient characteristics of CMOS inverters and gate circuits deteriorate due to the reduction of carrier mobilities and threshold voltages of MOS transistors and the increase of leakage currents of MOS transistors drain terminal pn junctions. The calculation results can explain the experimental phenomenon.
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Transient characteristic analysis of high temperature CMOS digital integrated circuits |
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| Ke Daoming,Feng Yaolan,Tong Qinyi,Ke Xiaoli. Transient characteristic analysis of high temperature CMOS digital integrated circuits[J]. Journal of Electronics, 1994, 11(2): 104-115. DOI: 10.1007/BF02778359 |
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| Authors: | Ke Daoming Feng Yaolan Tong Qinyi Ke Xiaoli |
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| Affiliation: | (1) Microelectronics Center Southeast University, 210018 Nanjing;(2) The Planning Committee of Hefei City, 230061 Hefei |
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| Abstract: | This paper analyses the transient characteristics of high temperature CMOS inverters and gate circuits, and gives the computational formulas of their rise time, fall time and delay time. It may be concluded that the transient characteristics of CMOS inverters and gate circuits deteriorate due to the reduction of carrier mobilities and threshold voltages of MOS transistors and the increase of leakage currents of MOS transistors drain terminal pn junctions. The calculation results can explain the experimental phenomenon. |
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| Keywords: | CMOS digital integrated circuits transient characteristics High temperature CMOS |
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