A power optimized 13-b 5 Msamples/s pipelined analog-to-digitalconverter in 1.2 μm CMOS |
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| Authors: | Cline D.W. Gray P.R. |
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| Affiliation: | Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA; |
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| Abstract: | A 13-b 5-MHz pipelined analog-to-digital converter (ADC) was designed with the goal of minimizing power dissipation. Power was reduced by using a high swing residue amplifier and by optimizing the per stage resolution. The prototype device fabricated in a 1.2 μm CMOS process displayed 80.1 dB peak signal-to-noise plus distortion ratio (SNDR) and 82.9 dB dynamic range. Integral nonlinearity (INL) is 0.8 least significant bits (LSB), and differential nonlinearity (DNL) is 0.3 LSB for a 100 kHz input. The circuit dissipates 166 mW on a 5 V supply |
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