High-voltage junction-gate field-effect transistor with recessed gates

A new recessed-gate structure for vertical-channel junction field-effect transistors (JFET's) is described together with a self-aligned gate-source process developed to fabricate these devices. Using this technology, devices with groove depths ranging from 8 to 18 µm have been fabricated. The characteristics of these devices is described as a function of the groove depth. It has been found that the devices display pentode-like characteristics at low gate voltages and triode-like characteristics at high gate voltages. The blocking gain has been found to increase with groove depth. However, this is accompanied by an increase in the on-resistance and a decrease in the saturated drain current. Devices with gate breakdown voltages of up to 600 V have been fabricated with the recessed-gate structure. These high-voltage field-effect transistors (FET's) have a unity power gain cutoff frequency of 600 MHz and gate turn-off times of less than 25 ns.