Fabrication of self-aligned 90-nm fully depleted SOI CMOS SLOTFETs |
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| Authors: | Chen C.K. Chen C.L. Gouker P.W. Wyatt P.W. Yost D.R. Burns J.A. Suntharalingam V. Fritze M. Keast L. |
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| Affiliation: | Lincoln Lab., MIT, Lexington, MA; |
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| Abstract: | We have developed a novel sub-100-nm fully depleted silicon-on-insulator (SOI) CMOS fabrication process, in which conventional 248-nm optical lithography and nitride spacer technology are used to define slots in a sacrificial layer (SLOTFET process). This process features a locally thinned SOI channel with raised source-drain regions, and a low-resistance T-shaped poly-Si gate; Both n- and p-channel MOSFETs with 90-nm gate length have been demonstrated. At a 0.5 V bias voltage, ring-oscillator propagation delay of less than 50 ps per stage has been measured |
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