DATA BYPASSING ARCHITECTURE AND CIRCUIT DESIGN FOR 32-BIT DIGITAL SIGNAL PROCESSOR

This paper presents a design method of ByPassing Unit（BPU） in 32-bit Digital Signal Processor（DSP）-MD32. MD32 is realized in 0.18 μm technology, 1.8V and 200 MHz working clock. It focuses on the Reduced Instruction Set Computer（RISC） architecture and DSP computation capability thoroughly, extends DSP with various addressing modes in a customized DSP pipeline stage architecture. The paper also discusses the architecture and circuit design of bypassing logic to fit MD32 architecture. The parallel execution of BPU with instruction decode in architecture level is applied to reduce time delay. The optimization of circuit that serial select with priority is analyzed in detail, and the result shows that about half of time delay is reduced after this optimization. Examples show that BPU is useful for improving the DSP＇s performance. The forwarding logic in MD32 realizes 8 data channels feedback and meets the working clock limit.

Data bypassing architecture and circuit design for 32-bit digital signal processor

This paper presents a design method of ByPassing Unit(BPU) in 32-bit Digital Signal Processor(DSP)-MD32. MD32 is realized in 0.18 μm technology, 1.8V and 200 MHz working clock. It focuses on the Reduced Instruction Set Computer(RISC) architecture and DSP computation capability thoroughly, extends DSP with various addressing modes in a customized DSP pipeline stage architecture. The paper also discusses the architecture and circuit design of bypassing logic to fit MD32 architecture. The parallel execution of BPU with instruction decode in architecture level is applied to reduce time delay. The optimization of circuit that serial select with priority is analyzed in detail, and the result shows that about half of time delay is reduced after this optimization. Examples show that BPU is useful for improving the DSP’s performance. The forwarding logic in MD32 realizes 8 data channels feedback and meets the working clock limit. Supported by the National High Technology Research & Development Program of China (863 Program) (2002AA1Z1140). Communication author: Chen Xiaoyi, born in 1978, male, doctoral student. Department of Electronic Engineering and Information Science, Zhejiang University, Hangzhou 310027, China.