基于同态映射的从UML导出可综合Verilog算法

UML建模因其可显著提高开发效率和代码质量已经成为软件开发领域的一大热点，而硬件设计的日益复杂性也要求我们在更高层次抽象上分析和验证系统行为，故更精细的系统级建模方法变得日趋重要。本文构建了UML元模型与可综合Verilog间的同态映射，定义了一个从UML模型子集导出可综合Verilog描述的算法，为UML模型对于建模硬件系统提供了形式化的语义，从而使运用UML进行硬件系统级建模和系统级上验证系统性能和功能正确性成为可能。

A Homomorphic Mapping Based Algorithm to Generate Synthesizable Verilog from UML

Modeling with UML has been a hot topic in software development domain since it can significantly improve product quality and productivity. But the constantly increasing complexity of hardware design also demands analysis and verification of system behavior on higher levels of abstraction, so more elaborate system - level modeling techniques are more and more important. In this paper, a homomorphic mapping between UML metamodel and synthesizable Verilog is constructed and a algorithm for deriving synthesizable Verilog specification from a subset of UML models is defined. So it is possible to use UML for hardware modeling and the performance and functionality correctness verifying at sys- tem level.