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H.264解码器的ASIC解决方案及其FPGA验证平台
引用本文:梁晓芸,焦孟草,林争辉.H.264解码器的ASIC解决方案及其FPGA验证平台[J].电视技术,2004(10):50-51,58.
作者姓名:梁晓芸  焦孟草  林争辉
作者单位:上海交通大学,电子信息学院,上海,200030;上海交通大学,电子信息学院,上海,200030;上海交通大学,电子信息学院,上海,200030
摘    要:论述了H.264解码器的ASIC(专用芯片)解决方案及其FPGA验证平台.该方案比常见DSP解决方案有更快的解码速度和更低的能耗,解决了H.264解码器由于算法复杂性增大带来的速度和能耗问题.鉴于大规模SoC芯片验证的复杂性,还比较详细地介绍了该芯片基于FPGA的验证平台.

关 键 词:H.264解码器  ASIC  片上系统  FPGA验证平台
文章编号:1002-8692(2004)10-0050-02

An ASIC Solution for H.264 Decoder and Its FPGA Verification Platform
LIANG Xiao-yun,JIAO Meng-cao,LIN Zheng-hui.An ASIC Solution for H.264 Decoder and Its FPGA Verification Platform[J].Tv Engineering,2004(10):50-51,58.
Authors:LIANG Xiao-yun  JIAO Meng-cao  LIN Zheng-hui
Abstract:This paper is about an ASIC (Application Specific Integrated Ciruit ) solution for H.264 decoder and its FPGA (Field Programmable Gate Array) verifi cation platform. This solution has faster decoding speed and less power consumpt ion, which greatly solves the problems of low speed and high power consumption d ue to the increased complexity of the algorithm of H.264 decoder. This paper als o introduces the FPGA verification platform in detail since verification is of c ritical importance for the success of a large scale SoC chip.
Keywords:ASIC
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