改进OR1200 CPU流水线的设计

流水线是制造高性能CPU的关键技术，目前被广泛研究的OR1200是一款带有四级流水线的免费开源CPU. 为了提高流水线的效率，针对OR1200没有设计访存流水段，流水线会暂停等待加载存储类指令这个问题，在LSU操作即访存操作模块，为OR1200增加了访存流水段，设计了冒险检测和旁路单元，因此CPU在访存阶段不需要暂停，从而使OR1200变为真正的五级流水线CPU；另一方面，当需要用加载指令加载数据的时候，会导致加载类数据冒险问题，为了解决此类冒险，设计了数据有效信号Tag，用来控制流水线暂停，对乘法计算、访存阶段以及其他不能在执行阶段得到结果的运算作流水线暂停判断，以等待数据的获取. 通过实验仿真证明，Tag信号暂停流水线一个时钟后会把数据反馈回去，成功解决了必须暂停数据相关问题的暂停判断问题.

Improved Design of Pipeline CPU Based on OR1200

The pipeline is the key technology of manufacturing high-performance CPU. The OR1200, which has been widely studied currently, is a 4-stage pipeline CPU with a free open source. Without MEM stage which should be designed in OR1200, the pipeline will be stalled to wait for load or store instruction. In this research, we design a MEM stage for OR1200 in LSU. Hazard detection and data forwarding units have been included for efficient implementation of the pipeline. On the other hand, when a data requested by a load instruction has not yet become available, it leads to load-use hazards. To resolve this hazard problem, we design a data valid signal Tag to control stalling of pipeline. The pipeline is stalled by the Tag signal for one stage and then continues with the forwarding of data, as the simulation result shows.