一种四阶锁相频率合成器的环路设计

重点讨论了四阶锁相频率合成器的环路滤波器的设计.环路滤波器主要采用有源比例积分滤波器,为获得更好的环路性能,采用了三阶环路滤波器.通过环路开环传递函数,得到了环路的时间常数和环路滤波器的元件的设计公式.对环路进行了仿真实验,实验结果和实际测试表明总体性能较好,能满足项目要求.

Design of Fourth-Order PLL Synthesizer

We introduced a fourth-order PLL synthesizer with emphasis on active loop filter(LF) in our work,which is constructive for improving the performance of PLL.The fourth-order loop restricts phase noise greatly by a third-order LF.We approached open-loop phase transfer function,evaluation formulae for parts of LF,and parameter time.The PLL synthesizer model was simulated and found to be credible.The synthesizer is tested to be satisfied.