A vertical submicron polysilicon thin-film transistor using a lowtemperature process |
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| Authors: | Tiemin Zhao Min Cao Saraswat KC Plummer JD |
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| Affiliation: | Center for Integrated Syst., Stanford Univ., CA ; |
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| Abstract: | This letter presents a submicron (0.5 μ) vertical N-channel MOS thin-film transistor (TFT) fabricated in Polycrystalline Si using a simple low temperature process (⩽600°C). The channel length is determined by the thickness of an SiO2 film. As a result, submicron vertical polysilicon TFT's can be fabricated without submicron lithographic equipment that is not yet available for large area active matrix liquid crystal display (AMLCD) applications. The device has a dynamic range of greater than five orders of magnitude after hydrogenation |
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