FPGA implementation of high-performance,resource-efficient Radix-16 CORDIC rotator based FFT algorithm |
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| Affiliation: | 1. Institute of Technology and Engineering, Indus University, Ahmedabad, Gujarat, India;2. Pandit Deendayal Petroleum University, Department of ICT, Gandhinagar, Gujarat, India;3. School of Engineering and Applied Science, Ahmedabad University, Ahmedabad, Gujarat, India;1. Department of Electronics and Communication Engineering, Thapar Institute of Engineering and Technology, Patiala, India;2. Computer Science and Engineering Department, Thapar Institute of Engineering and Technology, Patiala, India;3. School of Electronic Engineering and Computer Science, Queen Mary University of London, UK;1. Dep. Ingeniería Electrónica, E.T.S.I.Telecomunicación, Universidad Politécnica de Madrid, Spain;2. University CEU San Pablo, Spain;1. School of Engineering and Applied Science, Ahmedabad, India;2. Pandit Deendayal Petroleum University, Gandhinagar, India;3. Vishwakarma Government Engineering College, Ahmedabad, India |
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| Abstract: | The fast Fourier transform (FFT) is an algorithm widely used to compute the discrete Fourier transform (DFT) in real-time digital signal processing. High-performance with fewer resources is highly desirable for any real-time application. Our proposed work presents the implementation of the radix-2 decimation-in-frequency (R2DIF) FFT algorithm based on the modified feed-forward double-path delay commutator (DDC) architecture on FPGA device. Need for a complex multiplier to carry out the multiplication of complex twiddle factors and large memory to store the twiddle factors are the main concerns for FFT implementation. Propose work aims to address these issues. In this work, a high-performance radix-16 COordinate Rotational DIgital Computer (CORDIC) algorithm based rotator is proposed to carry out the complex twiddle factor multiplication. Further, CORDIC needs only rotational angles to carry out complex multiplication, which reduces the need for large memory to store the twiddle factors. To compute the total rotation for n-bit precision, our proposed radix-16 CORDIC algorithm takes n/4 iteration as compared to n iteration of the radix-2 CORDIC algorithm. Our proposed architecture of the radix-2 decimation-in-frequency (R2DIF) algorithm is implemented on a Virtex−7 series FPGA. Further, the detailed comparison is presented between our proposed FFT implementation and other recently proposed FFT implementations. Experimental results suggest that proposed implementation has less latency and hardware utilization as compared to recently proposed implementations. |
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| Keywords: | CORDIC algorithm FFT Double-path delay commutator (DDC) Canonical signed digit (CSD) Redundant arithmetic FPGA |
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