The synthesis method of logic circuits based on the iMemComp gates |
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| Affiliation: | 1. Key Lab of Integrated Microsystems, Peking University Shenzhen Graduate School, Shenzhen, 518055, China;2. Institute of Microelectronics, Peking University, Beijing, 100871, China;1. College of Information Science & Electronic Engineering, Zhejiang University, 38 Zheda Road, Hangzhou, 310027, China;2. The Department of Engineering Product Design, Singapore University of Technology and Design, 8 Somapah Road, Singapore, 487372, Singapore;3. The Department of Electrical Engineering and Computer Science, Lassonde School of Engineering, York University, Canada M4P 2A7;1. Department of Materials Science & Engineering, University of Tennessee, Knoxville, TN 37996, USA;2. Materials Science & Technology Division, Oak Ridge National Laboratory, Oak Ridge, TN 37831, USA;3. Pacific Northwest National Laboratory, P.O. Box 999, Richland, WA 99352, USA;1. School of Information Science and Engineering, Fudan University, 220 Handan Rd, Shanghai 20433, China;2. Key Laboratory for Information Science of Electromagnetic Waves (MoE), Fudan University, 220 Handan Rd, Shanghai 20433, China;2. Department of Electrical Engineering Technology, University of North Texas, Denton, TX 76207, USA;3. Department of Computer Science and Engineering, University of North Texas, Denton, TX 76207, USA |
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| Abstract: | The iMemComp is a family of logic gates based on RRAM devices. It has potential advantage on the design of high-performance logic circuits, since the NAND, AND, NOT and transmission iMemComp gates only consume single cycle, respectively. However, the synthesis method of logic circuits based on the iMemComp gates has not been systematically studied before. This work proposes the synthesis method of the row-oriented logic circuits based on the multi-input single-cycle iMemComp gates. The synthesis results show that the circuits generated from the proposed method outperform most of those RRAM based counterparts generated from the previous methods. Furthermore, the synthesis method of the array-oriented iMemComp logic circuits is proposed. The proposed array-oriented method generates the relatively high-performance logic circuits since both the row-based and the column-based single-cycle iMemComp gates are applied, and the generated circuits are relatively area-efficient because the intra-row and inter-row redundancies are utilized in the circuit mapping. |
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| Keywords: | RRAM iMemComp logic gates Synthesis method Logic circuits |
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