Hardware compression scheme based on low complexity arithmetic encoding for low power image transmission over WSNs |
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| Affiliation: | 1. TIMA Laboratory (CNRS, Grenoble INP, UJF), 46 Avenue Felix Viallet, 38031 Grenoble, France;2. Electronic and Microelectronic Laboratory, Sciences Faculty of Monastir, 5019 Monastir, Tunisia;3. College of Computer and Information Sciences, King Saud University, Saudi Arabia;1. School of Information Science and Technology, Kannur University, Mangattuparamba, 670567 Kannur, Kerala, India;2. School of Computer Sciences, Mahatma Gandhi University, Kottayam, Kerala, India;1. Department of Mathematics, Xidian University, Xi’an 710071, China;2. Institute of Graphics and Image Processing, Xianyang Normal University, Xianyang 712000, China |
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| Abstract: | Software implementation costs of most algorithms, designed for image compression in wireless sensor networks, do not justify their use to reduce the energy consumption and delay transmission of images. Even though the hardware solution looks to be very attractive for this problem, a specific care should be paid when designing a low power algorithm for image compression and transmission over these systems. The aim of this paper is to present and evaluate a hardware implementation for user-driven image compression scheme designed to respect the energy constraints of image transmission over wireless sensor networks (WSNs). The proposed encoder will be considered as a co-processor for tasks related with image compression and data packetization. In this paper, we discuss both of the hardware architecture and the features of this encoder circuit when prototyped on FPGA (field-programmable gate array) and ASIC (application-specific integrated circuit) circuits. |
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| Keywords: | Image compression Wireless sensor networks Low power VLSI |
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