基于施密特触发的高鲁棒性亚阈值标准单元

亚阈值电路是低功耗重要发展方向之一。随着电源电压降低，晶圆代工厂提供的标准单元电路性能容易受噪声和工艺偏差的影响，已经成为制约亚阈值芯片的瓶颈。该文提出一种基于施密特触发(ST)与反向窄宽度效应(INWE)的亚阈值标准单元设计方案。该方案首先利用ST的迟滞效应与反馈机制，在电路堆叠结点处添加施密特反馈管以优化逻辑门、减少漏电流、增强鲁棒性；然后，采用INWE最小宽度尺寸与分指版图设计方法，提高电路的开关阈值与MOS管的驱动电流；最后，在TSMC 65 nm工艺下构建标准单元的物理库、逻辑库和时序库，完成测试验证。实验结果表明，所设计的亚阈值标准单元与文献相比，功耗降低7.2%～15.6%，噪声容限提升11.5%～15.3%，ISCAS测试电路的平均功耗降低15.8%。

High-Robust Sub-threshold Standard Cells Using Schmitt Trigger

Sub-threshold circuit is an important development direction of low power consumption. With the reduction of power supply voltage, the performance of standard cell circuits provided by foundries is susceptible to noise and process deviations, which has become a bottleneck restricting sub-threshold chips. The high-robust sub-threshold standard cells are proposed in this work. The Schmitt Trigger (ST) and Inverse Narrow Width Effect (INWE) are used to improve the performance, leakage, robust of the logic gates. Then, the INWE minimum width size and finger layout methods are used to increase the switching threshold of the circuit and the drive current of transistor. Finally, the standard cell library is designed and verified with TSMC 65 nm process. The experimental results show that the power of designed standard cells is reduced about 7.2%～15.6%, the noise margin is improved about 11.5%～15.3%, and the average power of ISCAS test circuit is reduced about 15.8%.