自适应滤波器的FPGA实现

本文采用自上而下的设计思想,用FPGA实现了自适应滤波器.自适应滤波器选择FIR滤波器结构,采用了改进的LMS算法,从而使得在同样的硬件资源下滤波的速度可提高一倍;本论文用VHDL编写代码,用MaxplusII进行编译、综合和仿真,FPGA器件选用ALTERA公司的FLEX10K系列3万门的芯片,综合结果显示,所设计的自适应滤波器使用FLEX10K30的70%的资源;对综合后的网表进行了仿真,当时钟周期取40ns时,滤波器仍能够很好地消除噪声.

Implementation of Adaptive Filter with FPGA

An adaptive filter is realized with FPGA using top-down design idea in this paper. A FIR(finite impulse response) filter structure was used for it. Since an improved LMS (least mean square) algorithm was adopted, the operation speed of the proposed adaptive filter was twice of that of a standard LMS algorithm FIR filter. The adaptive filter was coded with VHDL, compiled and synthesized with ALTERA MaxplusII. A FLEX10K30 was selected for synthesizing, and the proposed adaptive filter occupied 70% resources of this chip. The proposed adaptive filter was simulated with MaxplusII, when the period of clock was 40ns, the filter could operate very well. The simulation results verified the correctness of the design.