| MVB总线中校验序列的编码设计 |
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| 引用本文： | 幸柒荣,林知明,温小旭.MVB总线中校验序列的编码设计[J].工业控制计算机,2009,22(9):59-60. |
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| 作者姓名： | 幸柒荣 林知明 温小旭 |
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| 作者单位： | 华东交通大学,江西,南昌,330013 |
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| 摘 要： | 基于CRC循环冗余校验和偶校验的基本原理，并根据TCN协议，在MVB总线中设计了一个由7位CRC校验码和1位偶校验位构成的具有双重校验的8住校验序列，大大提高了数据传输中的检错能力与可靠性。本设计采用QuartusII软件与VHDL语言实现，最终得到校验序列编鹆器的正确仿真波形，结果表明完全达到了预期的设计要求。
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| 关 键 词： | CRC 偶校验 MVB 校验序列 检错能力 |
Design of Check Sequence Encoding in MVB |
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| Abstract: | In this paper,based on the principle of CRC and even parity,and according to the TCN protocol,a 8-bit check sequence composed of a 7-bit CRC and a 1-bit even parity is designed in MVB,which greatly enhances its error detecting capability and reliability during the data transmission due to its duplication check.The check sequence encoding is described with VHDL language and Quartus II. |
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| Keywords: | CRC MVB |
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