| 65纳米工艺下逻辑综合阶段的低功耗策略 |
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| 引用本文： | 刘剑婷,林平分.65纳米工艺下逻辑综合阶段的低功耗策略[J].中国集成电路,2012(4):23-28,50. |
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| 作者姓名： | 刘剑婷 林平分 |
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| 作者单位： | 北京工业大学,北京市嵌入式系统重点实验室,北京100124 |
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| 摘 要： | 纳米工艺下ASIC芯片的功耗问题将成为未来设计的瓶颈。本文以SD卡Flash控制芯片为例,研究65纳米工艺下逻辑综合阶段降低功耗的手段及措施,分析这些手段对功耗的影响,最终确定最佳低功耗策略,并经流片验证该低功耗策略有效。
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| 关 键 词： | 65纳米 低功耗设计 逻辑综合 DC |
Low power methodology on logic synthesis level in 65nm process |
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| LIU Jian-ting,LIN Ping-fen.Low power methodology on logic synthesis level in 65nm process[J].China Integrated Circuit,2012(4):23-28,50. |
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| Authors: | LIU Jian-ting LIN Ping-fen |
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| Affiliation: | (Beijing Embedded System Key Lab, Beijing University of Technology, Beijing 100124, China) |
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| Abstract: | It shows that power consumption of ASIC chips is becoming the bottleneck of future design in DSM. This paper taking a case of Flash controller chip, research the low power methodology on logic synthesis level based on SMIC CMOS Logic 0.065um process technology, analysis the contributions of these methods to power decreasing, and finally work out the best low power methodology. The validity of this methodology is proved by the tapeout result. |
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| Keywords: | 65nm Low Power Design Logic synthesis DC |
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