基于改进YOLOv5的轻量级芯片封装缺陷检测方法

目的 针对芯片封装缺陷检测过程中检测精度低与模型难部署的问题，提出YOLOv5-SPM检测网络，旨在提高检测精度并实现模型轻量化。方法 首先，通过在特征提取模块后增加通道注意力机制，提高缺陷通道的关注度，减少冗余特征的干扰，进而提升目标的检测精度。其次，在主干网络与颈部网络连接处使用快速特征金字塔结构，更好地融合了自建芯片数据集的多尺度特征信息。最后，将主干网络的特征提取模块更换为MobileNetV3，将常规卷积更换为深度卷积和点卷积，有效降低了模型尺寸和计算量。结果 经过改进后的新网络YOLOv5s-SPM在模型参数下降29.5%的情况下，平均精度较原网络提高了0.6%，准确率提高了3.2%。结论 新网络相较于传统网络在芯片缺陷检测任务中实现了模型精度与速度的统一提高，同时由于模型参数减小了29.5%，更适合部署在资源有限的工业嵌入式设备上。

Lightweight Chip Package Defect Detection Method Based on Improved YOLOv5

The work aims to propose a YOLOv5-SPM detection network, solve the challenges concerning diminished detection accuracy and complex model deployment encountered in chip packaging defect detection, to enhance detection accuracy and facilitate the implementation of lightweight models. The channel attention mechanism was placed after each feature extraction module to increase the importance of defect-related channels, reduce the interference of redundant features and improve the target detection accuracy. Then, the SimSPPF pyramid pooling structure was used in the connection of the backbone network and the neck network to integrate multi-resolution features of the self-built chip data set more effectively. After that, the feature extraction module of the backbone network was replaced with MobileNetV3 and the conventional convolution was replaced with deep convolution and point convolution to significantly reduce the model size and calculation scale. The improved new network YOLOv5s-SPM achieved a 0.6% increase in mean average precision and a 3.2% increase in accuracy compared with the original network, while reducing the model parameters by 29.5%. The experimental results validate the superiority of the proposed network in achieving higher accuracy and faster detection speed in the task of chip defect detection. Since the model parameters are reduced by 29.5%, it can also be deployed on industrial embedded devices.