| 基于上下文的自适应二进制算术编码的硬件实现 |
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| 引用本文： | 陈光化,陆桂富,武凯.基于上下文的自适应二进制算术编码的硬件实现[J].微电子学与计算机,2006,23(11):16-18,25. |
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| 作者姓名： | 陈光化 陆桂富 武凯 |
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| 作者单位： | 上海大学,自动化系,上海,200072 |
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| 基金项目： | 上海市重点学科建设项目 |
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| 摘 要： | 文章提出了一种适用H.264标准的自适应算术编码器的VLSI实现方案,它对算术编码的结构做了改进,用查表代替了乘法操作,并采用流水线结构实现,获得了较高的吞吐速率.在采用Verilog语言对编码模块进行描述后,用ALTEAR公司的现场可编程门阵列（FPGA）进行仿真验证.实验表明,这种流水线结构的算术编码器能够获得较高的编码速度.
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| 关 键 词： | 算术编码 流水线 |
| 文章编号： | 1000-7180（2006）11-0016-03 |
| 收稿时间： | 2005-11-01 |
| 修稿时间： | 2005-11-01 |
A Hardware Implementation of Context-based Adaptive Binary Arithmetic Coding |
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| CHEN Guang-hua,LU Gui-fu,WU Kai.A Hardware Implementation of Context-based Adaptive Binary Arithmetic Coding[J].Microelectronics & Computer,2006,23(11):16-18,25. |
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| Authors: | CHEN Guang-hua LU Gui-fu WU Kai |
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| Affiliation: | Department of Automation. Shanghai University, Shanghai 200072 |
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| Abstract: | VLSI implementation of Context-based Adaptive Binary Arithmetic Coding in H.264 is presented in this paper. We use a pre-computed lookup table to implement multiplication operation in arithmetic coding. Pipeline in this design is used to improve the speed of the throughput. It is described with Verilog language,and the arithmetic coder is implemented on the ALTERA FPGA. Simulation results show that this kind of arithmetic coder with pipeline architecture can achieve a good coding speed. |
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| Keywords: | FPGA |
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