首页 | 本学科首页   官方微博 | 高级检索  
     

Cache自适应写分配策略
引用本文:郇丹丹, 李祖松, 胡伟武, 刘志勇. Cache自适应写分配策略[J]. 计算机研究与发展, 2007, 44(2): 348-354.
作者姓名:郇丹丹  李祖松  胡伟武  刘志勇
作者单位:中国科学院计算技术研究所计算机系统结构重点实验室,北京,100080;中国科学院研究生院,北京,100049;中国科学院计算技术研究所计算机系统结构重点实验室,北京,100080
基金项目:国家自然科学基金 , 国家高技术研究发展计划(863计划) , 国家重点基础研究发展计划(973计划) , 国家自然科学基金
摘    要:处理器所能提供的有效带宽是目前制约处理器性能提高的关键因素.通过对Cache写失效行为的分析,提出了一种新的提高处理器带宽利用率的Cache写失效处理策略——Cache自适应写分配策略.该策略在访存失效队列中收集全修改Cache块,对全修改Cache块采用非写分配策略,并能够自适应地切换为写分配策略.与传统的Cache写失效处理策略相比,Cache自适应写分配策略硬件代价小,避免了不必要的数据传输,降低Cache污染,减少存储管理队列阻塞的频率.结果表明,采用Cache自适应写分配策略,STREAM基准测试程序带宽平均提高62.6%,SPEC CPU2000程序的IPC值平均提高5.9%.

关 键 词:Cache  写失效  写分配  带宽  龙芯2号
修稿时间:2005-11-23

A Cache Adaptive Write Allocate Policy
Huan Dandan, Li Zusong, Hu Weiwu, Liu Zhiyong. A Cache Adaptive Write Allocate Policy[J]. Journal of Computer Research and Development, 2007, 44(2): 348-354.
Authors:Huan Dandan  Li Zusong  Hu Weiwu  Liu Zhiyong
Affiliation:1 Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100080; 2 Graduate University of Chinese Academy of Sciences, Beijing 100049
Abstract:The bandwidth becomes the major bottleneck of the performance improvement for modern microprocessors. A cache adaptive write allocate policy that improves the bandwidth of microprocessor significantly is proposed by investigating cache store misses. The cache adaptive write allocate policy collects fully modified blocks in miss queue. Fully modified blocks are written to lower level memory based on non-write allocate policy which can switch to write allocate policy adaptively. Compared with other cache store miss policies, the cache adaptive write allocate policy avoids unnecessary memory traffic, reduces cache pollution and decreases load & store queue full rate without increasing hardware overhead. Experiment results indicate that on average 62.6% memory bandwidth in STREAM benchmarks is improved by utilizing the cache adaptive write allocate policy. The performance of SPEC CPU 2000 benchmarks is also improved efficiently. The average IPC speedup is 5.9%.
Keywords:cache  store miss  write allocate  bandwidth  Godson-2
本文献已被 CNKI 维普 万方数据 等数据库收录!
点击此处可从《计算机研究与发展》浏览原始摘要信息
点击此处可从《计算机研究与发展》下载全文
设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司  京ICP备09084417号