Intrinsic reliability projections for a thin JVD silicon nitridegate dielectric in P-MOSFET |
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Authors: | Polishchuk I Qiang Lu Yee-Chia Yeo Tsu-Jae King Chenming Hu |
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Affiliation: | Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA; |
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Abstract: | A comprehensive study of the intrinsic reliability of a 1.4-nm (equivalent oxide thickness) JVD Si3N4 gate dielectric subjected to constant-voltage stress has been conducted. The stress leads to the generation of defects in the dielectric. As a result, the degradation in the threshold voltage, subthreshold swing, gate leakage current, and channel mobility has been observed. The change in each of these parameters as a function of stress time and stress voltage is studied. The data are used to project the drift of a MOSFET incorporating JVD nitride at a low operating voltage of 1.2 V in 10 years. Based on these projections, we conclude that the increase in the Si3N4 gate dielectric leakage current does not pose a serious threat to device performance. Instead, the degradation in the threshold voltage and channel mobility can become the factor limiting the device reliability |
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