| USB3.0设备控制器IP核OUT端点测试平台的研究与实现 |
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| 引用本文： | 吴从中,彭乐,王亚君,尹夕振. USB3.0设备控制器IP核OUT端点测试平台的研究与实现[J]. 电子测量与仪器学报, 2012, 26(7): 646-651 |
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| 作者姓名： | 吴从中 彭乐 王亚君 尹夕振 |
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| 作者单位： | 1. 合肥工业大学计算机与信息学院,合肥,230009
2. 合肥云宇信息科技有限公司,合肥,230088 |
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| 摘 要： | 从一款自主研发的USB3.0设备控制器IP核出发,完成USB3.0设备控制器IP核OUT端点模块3种传输模式(批量传输、中断传输和等时传输)的功能验证。通过Verilog语言搭建一个完整的OUT端点测试平台,测试平台包括USB3.0设备控制器IP核、主机模块(包参数产生模块、包产生模块、链路命令产生模块、包检测模块及链路命令检测模块)和应用核模块。实验测试结果与USB3.0 OUT端点3种传输模式的协议规范完全符合。该平台能够对USB3.0设备控制器IP核OUT端点的3种传输方式进行全方位的功能验证。
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| 关 键 词： | USB3.0设备控制器 IP核 OUT端点 测试平台 功能验证 |
Research and implementation of OUT endpoint test bench for USB3.0 device controller IP core |
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| Wu Congzhong , Peng Le , Wang Yajun , Yin Xizhen. Research and implementation of OUT endpoint test bench for USB3.0 device controller IP core[J]. Journal of Electronic Measurement and Instrument, 2012, 26(7): 646-651 |
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| Authors: | Wu Congzhong Peng Le Wang Yajun Yin Xizhen |
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| Affiliation: | 1(1.School of Computer and Information,Hefei University of Technology,Hefei 230009,China; 2.Hefei Yunyu Information Technology Ltd.Co.,Hefei 230088,China) |
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| Abstract: | Based on a self-developed USB3.0 device controller IP core to test the function of the USB3.0 device IP core out endpoint.A test bench is built using Verilog language.The test bench simulates USB3.0 host and USB3.0 appli-cation(core) including USB3.0 host(packet parameter generate module,packet generate module,link command generate module,packet check module and link command check module),USB3.0 device controller IP core,and USB3.0 applica-tion core.The test results fully accord with the specification of USB3.0 OUT endpoint.The test-bench has successfully verified all required transfer(bulk transfer,interrupt transfer,and isochronous transfer) for the out endpoint of USB3.0 device controller IP core. |
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| Keywords: | USB3.0 device controller IP core OUT endpoint test bench functional verification |
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