Low power dynamic circuit for power efficient bit lines |
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| Affiliation: | 1. School of Engineering, Damghan University, Damghan, Iran;2. Department of Electrical Engineering, Shahrood University of Technology, Shahrood, Iran;1. Department of Electronics Instrumentation and Control Engineering, Government Engineering College, Ajmer 305025, India;2. Department of Electronics and Communication Engineering, Government Engineering College, Ajmer 305025, India;3. Department of Electronics and Communication Engineering, Malaviya National Institute of Technology, Jaipur 302017, India;1. School of Electronic and Information Engineering, Nanjing University of Information Science and Technology, Nanjing, Jiangsu 210044, China;2. Department of Microwave and Millimeter Wave Modules, Nanjing Electronic Devices Institute, Nanjing, Jiangsu 210016, China;1. Department of Electrical Engineering, Vali-E-Asr University of Rafsanjan, Rafsanjan, Iran;2. Microwave & Millimeter Wave Research Group, Electrical Engineering Department, Shahid Bahonar University of Kerman, Iran;3. Department of Electrical Engineering, Shahid Bahonar University of Kerman, Kerman, Iran;1. Unité de Recherche d’Automatique et Informatique Appliquée (LAIA), Department of Electrical Engineering, IUT-FV Bandjoun, University of Dschang, Cameroon;2. Unité de Recherchede Matière Condensée, d''Electronique et de Traitement du Signal (LAMACETS), Department of Physics, University of Dschang, P.O. Box 67, Dschang, Cameroon |
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| Abstract: | In this paper, a low power dynamic circuit is presented to reduce the power consumption of bit lines in multi-port memories. Using the proposed circuit, the voltage swing of the pull-down network is lowered to reduce the power consumption of wide fan-in gates employed in memory’s bit lines. Wide fan-in OR gates are designed and simulated using the proposed dynamic circuit in 90 nm CMOS technology. Simulation results show at least 40% reduction of power consumption and 1.2X noise immunity improvement compared to the conventional dynamic circuits at the same delay. Exploiting the proposed dynamic circuit, wide fan-in multiplexers are also designed. The multiplexers are simulated using a 90 nm CMOS model in all process corners. The results show 41% power reduction and 27% speed improvement for the proposed 128-input multiplexer in comparison with the conventional multiplexer at the same noise immunity. |
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| Keywords: | Dynamic logic Wide fan-in gates Noise immunity Bit lines |
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