A 5-bit 1.8 GS/s ADC-based receiver with two-tap low-overhead embedded DFE in 130-nm CMOS |
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| Affiliation: | 1. Laboratory of Optical Materials and Structures, Institute of Semiconductor Physics, SB RAS, Novosibirsk 630090, Russia;2. Functional Electronics Laboratory, Tomsk State University, Tomsk 634050, Russia;3. Laboratory of Single Crystal Growth, South Ural State University, Chelyabinsk 454080, Russia;4. Radio-Received and Radio-Transmitted Devices Department, Novosibirsk State Technical University, Novosibirsk 630073, Russia;5. Department of Electronic Devices, Novosibirsk State Technical University, Novosibirsk 630073, Russia;6. General Physics Department, Novosibirsk State Technical University, Novosibirsk 630073, Russia;1. Dept. of Electronics and Communication Engg, Institute of Engineering and Management (IEM), Gurukul Campus, Sector V, Kolkata, WB 700 091, India;2. Department of Electronics and Tele-Communication Engineering, Jadavpur University, Kolkata 700 032, India;1. College of Astronautics, Nanjing University of Aeronautics and Astronautics, Nanjing 210016, China;2. State Key Laboratory of Integrated Service Networks, Xidian University, Xi’an 710071, China |
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| Abstract: | Along with CMOS technology scaling, ADC-based serial link receivers have drawn growing interest in backplane communications but power dissipation of the ADC and complex digital equalizer in such digital receivers can be a limiting factor in high-speed applications. Implementing analog embedded equalization within the front-end ADC structure can potentially relax the ADC resolution requirement and reduces the complexity of the DSP which results in a more energy-efficient receiver. In this paper, the equivalence between the speculative comparisons of a loop-unrolling DFE and an ADC with non-uniform quantization levels is utilized to propose a novel ADC-based DFE receiver structure. The equivalency partially compensates for the power overhead imposed by loop-unrolling DFE. The 5-bit prototype receiver with two-tap embedded DFE is designed, laid out and simulated in a 130-nm CMOS process with 1.8 Gbps data rate. With embedded DFE disabled, the receiver achieves 4.57-bits ENOB and 1.77 pJ/conv.-step FOM. With 1.8-Gbps signaling across a 48-in FR4 channel, the two-tap DFE enabled receiver opens the completely closed eye and allows for a 0.26 UI timing margin at a BER of 10?9. The total active area is 0.21 mm2 and the ADC consumes 76 mW from a 1.2-V supply. |
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| Keywords: | Analog-to-digital converter Serial link receiver Decision feedback equalization (DFE) Analog DFE Flash ADC |
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