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A hybrid NMOS/PMOS capacitor-less low-dropout regulator with fast transient response for SoC applications
Affiliation:1. Department of Electrical Engineering, Minia University, Minia, Egypt;2. Electronics and Electrical Communications Engineering, Cairo University, Giza, Egypt;3. Department of Electrical Engineering, Aswan University, Aswan, Egypt;1. Electronic Engineering Department, University of Seville, Seville 41092, Spain;2. Klipsch School of Electrical Engineering, New Mexico State University, Las Cruces 88003-0001, USA;1. Department of Electrical Engineering, University of Guilan, Rasht, Iran;2. Department of Electronic Engineering, Technical University of Catalunya, Barcelona, Spain;1. Benemérita Universidad Autónoma de Puebla, Ciudad Universitaria, Puebla, Mexico;2. Universidad Iberoamericana, Blvrd del Niño Poblano 2901, San Andrés Cholula, Puebla, Mexico;3. Universidad Veracruzana, Av. Juan Pablo II S/N, Costa Verde, 94292, Boca Del Rio, Veracruz, Mexico;4. Instituto Nacional de Astrofísica, Optica y Electrónica, Luis Enrique Erro 1, Tonantzintla Puebla, Mexico;1. School of Physics & Electronic Engineering, Guangzhou University, Guangzhou, China;2. Institute of Election & Communication, Sun Yat-sen University, Guangzhou, China
Abstract:In this paper, a new architecture of a fully integrated low-dropout voltage regulator (LDO) is presented. It is composed of hybrid architecture of NMOS/PMOS power transistors to relax stability requirements and enhance the transient response of the system. The LDO is capable of producing a stable output voltage of 1.1 V from 1.3 V single supply with recovery settling time about 680 nsec. It can supply current from 10 µA to 100 mA consuming quiescent current of 20.5 µA and 95 µA, respectively. It supports load capacitance from 0 to 50 pF with phase margin that increases from 43° at low load (10 µA) to 74° at high load (100 mA) and power supply rejection ratio (PSRR) less than −20 dB up to 100 kHz. The proposed LDO is designed in 130 nm CMOS technology and occupies an area of 0.11 mm2. Post layout simulations show better performance compared with other reported techniques.
Keywords:Low-dropout regulator  Capacitor-less LDO  Fast transient response  System-on-chip (SoC)
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