| 串行RapidIO验证模型 |
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| 引用本文： | 谢智勇,罗明,蒋俊.串行RapidIO验证模型[J].计算机工程,2008,34(Z1). |
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| 作者姓名： | 谢智勇 罗明 蒋俊 |
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| 作者单位： | 华东计算技术研究所,上海,200233 |
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| 摘 要： | 片上系统设计中大量使用IP核,其验证是整个系统设计的关键.串行RapidIO(SRIO)定义了器件间的全双工串行链路,物理上每个方向使用单向差分信号,因此SRIO核的验证存在一定的难度.该文基于PCI-RapidIO桥的设计与实现,建立了SRIO的验证模型,包括功能仿真模型、硬件验证模型和互操作性验证模型,为SRIO核的验证提供了思路,并建立了SRIO的仿真环境平台和FPGA硬件验证平台.
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| 关 键 词： | 验证 PCI-RapidIO 桥 |
Verification Model of Serial RapidIO |
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| XIE Zhi-yong,LUO Ming,JIANG Jun.Verification Model of Serial RapidIO[J].Computer Engineering,2008,34(Z1). |
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| Authors: | XIE Zhi-yong LUO Ming JIANG Jun |
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| Affiliation: | XIE Zhi-yong,LUO Ming,JIANG Jun (East China Institute of Computer Technology,Shanghai 200233) |
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| Abstract: | A great deal of IP cores are used in SoC design,so the verification of the IP core is the key of entire system design.There are some difficult in verifying SRIO,because it defines full duplex link between two devices,and employs unidirectional differential signal in each direction in physics.This paper establishes the verification model of SRIO,including function simulation model,hardware testing and interoperability testing based on the design and implementation of PCI-RapidIO bridge.It gives some methods ... |
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| Keywords: | RapidIO |
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