锁相环相位噪声的研究与仿真

锁相环在数字电路中一个重要的应用就是作为频率合成器产生高性能的时钟。本文介绍了锁相环的工作原理,重点研究了锁相环输出时钟的相位噪声的影响因素。通过对其线性环路模型进行频域分析,运用反馈控制理论,讨论了环路内各器件的噪声对其输出信号相位噪声的影响。得到了锁相环能良好改善环路带内噪声的分析结果,并且利用ADS搭建仿真电路,验证分析结果,为今后高性能频率合成器的设计和应用提供参考依据。

Research and simulation of phase noise in PLL

One important application of Phase locked loops in digital circuits is worked as frequency synthesizers to generate a highly reliable clock.The PLL's theory is introduced and the factors of the phase noise of the output clock are focused.The linear loop model is analyzed;the influence of noise from every component in the loop is discussed by feedback control theory.The result is that PLL can restrain the noise in the loop.And the simulation is implemented using ADS according to the analysis and the result i...