The study of threshold voltage extraction of nitride spacer NMOS transistors in early stage hot carrier stress |
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Authors: | Jun-Lin Tsai Kai-Ye Huang Jinn-Horng Lai Jeng Gong Fu-Jei Yang Sun-Yun Lin |
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Affiliation: | Inst. of Electron. Eng., Nat. Tsing Hua Univ., Hsinchu; |
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Abstract: | Threshold voltage V/sub t/ extracted by g/sub m/-maximum extrapolation method under early stage hot carrier stress is proven to be an inappropriate method once electrons are trapped in a nitride spacer. The trapping of electrons in a nitride spacer increases the series drain resistance, reducing the transconductance g/sub m/ and the corresponding gate-to-source voltage V/sub gs/ at which peak g/sub m/ occurs. It ultimately decreases the threshold voltage V/sub t/ extracted by the g/sub m/-maximum extrapolation method. A novel algorithm is derived to determine the relationship between the measured data and the true threshold voltage of such a device under hot carrier stress by considering the effect of series resistance in g/sub m/-maximum extrapolation method. |
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