Via-filling using electroplating for build-up PCBs |
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Affiliation: | 1. Electro-Materials Research Laboratory, Centre for Nanoscience and Technology, Pondicherry University, Puducherry 605014, India;2. School of Materials Science and Engineering, National Institute of Technology Calicut, Kozhikode 673601, India;3. School of Materials Science and Engineering, Jiangsu University of Science and Technology, Zhenjiang 212003, China;4. Department of Chemistry, Christ University, Bangalore 560029, India |
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Abstract: | The requirement of miniaturization of printed circuit boards has been increased with downsizing of electronic devices. However, the conventional multi-layered printed circuit boards are now facing the limitation for high mounting densities. Therefore, a newly developed build-up process has emerged as a new multi-layered printed circuit board manufacturing process. This new technology has adopted the micro-vias for connection between each conductive layer. If the micro-vias can be filled with copper metal, signal propagation is enhanced by via-on-via connection. Therefore, effective circuitry can be achieved. However, filling the conductive layer with the micro-vias is becoming difficult using the conventional plating process or the electrical conductive paste. Filling of the micro-vias by electroplating is studied. It was confirmed that copper sulfate concentration in copper sulfate plating bath is one of the key factors to fill the micro-vias, and the vias can be filled using a high copper concentration bath. |
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