应用于堆叠纳米线MOS器件的STI工艺优化研究

在传统Fin FET集成工艺上, 通过Ge Si/Si叠层量子阱结构外延生长再形成堆叠纳米线MOS场效应晶体管的方案, 是实现5 nm及其以下CMOS集成电路工艺技术最具可能的器件方案。由于Ge元素在该技术中的引入, 导致器件工艺中的浅沟槽隔离 (STI) 工艺部分产生严重的低温高深宽比工艺 (HARP) SiO₂腐蚀速率控制问题。本文针对堆叠纳米线MOS器件STI工艺中的低温HARP SiO₂回刻腐蚀速率调节与均匀性控制问题, 进行了全面的实验研究。实验中使用HF溶液对不同工艺条件下的HARP SiO₂进行回刻腐蚀, 并对其腐蚀速率变化进行了详细研究, 具体包括不同退火时长以及相同退火温度不同厚度HARP SiO₂位置处的腐蚀速率。通过实验结果发现, 在退火温度相同的情况下, 随着退火时长的增加, SiO₂腐蚀速率逐渐变小;而对于同一氧化层来说, 即使退火条件相同, SiO₂不同厚度位置处的腐蚀速率表现也不同, 即顶部的速率最大, 而底部则最小。由此可以看出, 随着退火时长的增加, 低温HARP SiO₂腐蚀速率逐渐减小, 并且对STI具有深度依赖性。该实验结果对成功制作5 nm技术代以下堆叠纳米线器件的STI结构起到了重要的技术支撑作用。

Optimization of Shallow Trench Isolation in Fabrication of Stacked Nanowire MOS Devices

Herein, we experimentally addressed the uniformity control and regulation of low-temperature Si_O2 etch-back corrosion-rate in high aspect ratio process (HARP) in forming shallow trench isolation (STI) for the stacked nanowire MOS devices with feature size of and/or below 5 nm. The influence of the annealing temperature/time and SiO₂ thickness, on the SiO₂ corrosion-rate, etched back with HF solution in low temperature HARP, was investigated. The results show that the annealing time and SiO₂ thickness had a major impact. For example, as the annealing time (at a fixed annealing temperature) increased, the SiO₂ corrosion-rate decreased; depending on the thickness, the SiO₂ corrosion-rate, in the same layer, was maximized at the top and minimized at the bottom. We suggest that the results reported here be of some technological interest in fabrication of STI structure of stacked nanowire devices with a feature-size of and/or below 5 nm.