A shallow buried-layer formation technique utilizing diffusion fromimplanted polysilicon layer

A shallow buried-layer (0.25~0.50 μm) formation technique utilizing diffusion from an arsenic-implanted polysilicon layer is discussed. The polysilicon layer is removed by converting it into an oxide layer and wet etching the oxide layer. Vertical n-p-n bipolar transistors are fabricated on epitaxial layers deposited on buried layers formed utilizing this technique. The transistor characteristics indicate that high-quality epitaxial layers can be grown on these buried layers. Using this technique, a buried layer with a sheet resistance of 28 Ω/□ and a junction depth of ~0.4 μm was obtained (prior to the epitaxial growth)