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Simulation and Experimental Evaluation of a Soft Error Tolerant Layout for SRAM 6T Bitcell in 65nm Technology |
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| Authors: | Lixiang Li Yuanqing Li Haibin Wang Rui Liu Qiong Wu Michael Newton Yuan Ma Li Chen |
| Affiliation: | 1. Department of Electrical and Computer Engineering, Dalhousie University, 1360 Barrington Street, Halifax, NS, Canada 2. Department of Electrical and Computer Engineering, University of Saskatchewan, 57 Campus Drive, Saskatoon, SK, Canada 3. College of IOT Engineering, Hohai University, Changzhou, 213022, China 4. College of Information and Control Engineering, China University of Petroleum, Qingdao, China |
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| 本文献已被 SpringerLink 等数据库收录！ | |