Design of fully integrated programmable PLL frequency synthesizers for microprocessor clocking at 1–1500 MHz

This paper is concerned with the design of fully integrated programmable PLL frequency synthesizers for microprocessor clocking at 1–1500 MHz. The focus is on the circuit configuration and performance parameters of the basic analog units of the PLL: the stabilized bias unit, phase-frequency detector, charge pump, loop filter, and voltage-controlled oscillator (VCO). The data examined are obtained by measurements on ICs fabricated by a 0.25-or 0.18-μm established CMOS technology. The circuit configurations are presented of VCOs that are tunable up to 1–1.3 GHz or up to over 2 GHz; they are designed to be implemented in a 0.25-or 0.18-μm technology, respectively. Also addressed is the design of the digital section of PLL synthesizers with a tuning range extending from 1 to over 1000 MHz. The PLL frequency and step responses, current consumption, and jitter performance are presented and investigated.