Drain structure optimization for highly reliable deep submicrometern-channel MOSFET

A guideline for n^- fully gate overlapped (FOLD) structure design optimization has been studied. From the viewpoint of reliability, the greatest reduction in substrate current directly leads to the most reliable n^- design for the FOLD structure. The current path modulation phenomenon due to the trapped charge at the n ^- extension region dominates the hot-carrier induced characteristics change for conventional lightly doped drain (LDD) structure with side-wall spacer. This phenomenon is minimized in the FOLD structure due to its higher controllability of the gate electrode than the LDD structure at the n^- extension region. Furthermore, it was also confirmed that the 0.3 μm optimized FOLD structure can achieve high circuit performance at 3.3 V operation, maintaining hot-carrier resistance