| 语音增强算法的FPGA实现 |
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| 引用本文： | 叶利剑,黄松华,王尧,邱小军. 语音增强算法的FPGA实现[J]. 电声技术, 2010, 34(1): 67-70 |
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| 作者姓名： | 叶利剑 黄松华 王尧 邱小军 |
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| 作者单位： | AAC声学科技有限公司南京研发中心,江苏,南京,210009;南京大学声学研究所,江苏,南京,210093 |
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| 摘 要： | 介绍了语音增强谱减算法的原理，设计并实现了基于FreeDev公司Altera CycloneⅡ开发板的FPGA语音增强谱减算法片上实时系统。系统使用Altera提供的SOPC Builder及IP核进行硬件系统设计，在NiosⅡIDE开发环境下编写软件工程。实验结果表明，采用FPGA实现语音增强算法系统是有效的。
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| 关 键 词： | FPGA Nios FFT IP核 语音增强 |
Implementation of Speech Enhancement Algorithm on FPGA |
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| YE Li-jian,HUANG Song-hu,WANG Yao,QIU Xiao-jun. Implementation of Speech Enhancement Algorithm on FPGA[J]. Audio Engineering, 2010, 34(1): 67-70 |
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| Authors: | YE Li-jian HUANG Song-hu WANG Yao QIU Xiao-jun |
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| Affiliation: | 1. AAC Acoustic R＆D Centre (Nanjing), Nanjing 210009, China 2. Institute of Acoustics, Nanjing University, Nanjing 210093, China ) |
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| Abstract: | The principle of a spectral subtraction speech enhancement algorithm is presented. The realtime system on chip speech enhancement system is designed and implemented using FreeDev Audio FPGA development board of Altera Cyclone II FPGA. The hardware design is based on the SOPC Builder and IP cores, and the software is compiled on the Nios II IDE. Experimental result indicates that it is feasible to implement the speech enhancement system implemented on FPGA. |
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| Keywords: | FPGA Nios II FFT IP core speech enhancement |
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