| 基于FPGA的数字乘法器性能比较 |
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| 引用本文： | 马昕,鞠芳,田岚.基于FPGA的数字乘法器性能比较[J].电子器件,2011,34(6):718-722. |
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| 作者姓名： | 马昕 鞠芳 田岚 |
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| 作者单位： | 山东大学信息科学与工程学院 |
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| 基金项目： | 山东省中青年科学家科研奖励基金:基于光纤激光技术的丰富音感知仿生耳系统研究(2010BSE27237) |
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| 摘 要： | 详细描述了四种基本的FPGA数字乘法器设计方法即阵列法、查找表法、移位相加法、Booth法的原理和实现过程.以4×4和16×16数字乘法器的设计为例,通过在AlteraFPGA芯片上的仿真与综合,给出了这四种数字乘法器的运算速度和占用逻辑资源情况.结果表明随着位宽的变化,各方法的相对效果会有变化,对于具有较宽数据位的乘...
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| 关 键 词： | 数字乘法器 FPGA Booth方法、移位相加法 |
Performance Comparisons for FPGA-based Digital Multipliers |
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| JU Fang,MA Xin,TIAN Lan.Performance Comparisons for FPGA-based Digital Multipliers[J].Journal of Electron Devices,2011,34(6):718-722. |
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| Authors: | JU Fang MA Xin TIAN Lan |
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| Affiliation: | (College of Information Science & Engineering,Shandong University,Jinan 250100,China) |
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| Abstract: | The principles and realizing processes of four kinds of FPGA digital multipliers which are named array,look-up table,shift-add and Booth are described in detail.By simulation and synthesizing of the four kinds of FPGA digital multipliers in Altera FPGA chip,the performances in speed and resources consumption are also presented with 4×4 and 16×16 digital multipliers as examples.The results show the Booth multiplier has evident advantages when Multiplier has larger data width while the shift-add multiplier can economize resources in chip. |
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| Keywords: | digital multiplier FPGA computing speed logic resources consumption |
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