A 16-bit 1 MSPS SAR ADC with foreground calibration and residual voltage shift strategy |
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| Xian Zhang, Xiaodong Cao, Xuelian Zhang. A 16-bit 1 MSPS SAR ADC with foreground calibration and residual voltage shift strategy[J]. Journal of Semiconductors, 2020, 41(12): 122401. doi: 10.1088/1674-4926/41/12/122401 X Zhang, X D Cao, X L Zhang, A 16-bit 1 MSPS SAR ADC with foreground calibration and residual voltage shift strategy[J]. J. Semicond., 2020, 41(12): 122401. doi: 10.1088/1674-4926/41/12/122401.Export: BibTex EndNote |
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| Authors: | Xian Zhang Xiaodong Cao Xuelian Zhang |
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| Affiliation: | 1. University of Chinese Academy of Sciences, Beijing 100049, China;2. Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China |
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| Abstract: | In this paper, a 16-bit 1MSPS foreground calibration successive approximation register analog-to-digital converter (SAR ADC) is developed by the CMOS 0.25 μm process. An on-chip all-digital foreground weights calibration technique integrating self-calibration weight measurement with PN port auto-balance technique is designed to improve the performance and lower the costs of the developed SAR ADC. The SAR ADC has a chip area of 2.7 × 2.4 mm2, and consumes only 100 μW at the 2.5 V supply voltage with 100 KSPS. The INL and DNL are both less than 0.5 LSB. |
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| Keywords: | foreground all-digital calibration RS strategy RS-based dither auto-zero comparator SAR ADC |
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