A VLSI structure for the deadlock avoidance problem |
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| Authors: | P. Bertolazzi G. Bongiovanni |
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| Affiliation: | Istituto di Analisi dei Sistemi ed Informatica del CNR, Viale Manzoni 30, 00185 Rome, Italy;Istituto Guido Castelnuovo, Università di Roma, Piazzale Aldo Moro 4, 00185 Rome, Italy |
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| Abstract: | In this paper we present two VLSI structures implementing the banker's algorithm for the deadlock avoidance problem, and we derive the area x (time)2 lower bound for such an algorithm. The first structure is based on the VLSI mesh of trees. The second structure is a modification of the first one, and it approaches more closely the theoretical lower bound. |
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