| 高性能通用微处理器体系结构关键技术研究 |
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| 引用本文： | 张民选,王永文,邢座程,邓让钰,蒋江,张承义.高性能通用微处理器体系结构关键技术研究[J].计算机研究与发展,2006,43(6):987-992. |
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| 作者姓名： | 张民选 王永文 邢座程 邓让钰 蒋江 张承义 |
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| 作者单位： | 国防科学技术大学计算机学院,长沙,410073 |
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| 基金项目： | 中国科学院资助项目;国家科技攻关项目 |
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| 摘 要： | X处理器是我国自主设计的基于EPIC思想的高性能通用微处理器．介绍了8级流水线和OLSM执行模型，以很少的硬件代价克服了基本EPIC模型的局限性．设计了一种多分支预测结构，支持多条分支指令的并行执行，并通过判定执行减少分支指令的数目；设计了两级cache存储器，提出DTD低功耗设计方法，并通过前瞻执行隐藏访存的延迟．最后，展望了高性能通用微处理器的发展趋势．
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| 关 键 词： | 微处理器 体系结构 并行 分支 存储器 |
| 收稿时间： | 07 11 2005 12:00AM |
| 修稿时间： | 2005-07-112006-01-10 |
Research on High Performance General Purpose Microprocessor Architecture |
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| Zhang Minxuan,Wang Yongwen,Xing Zuocheng,Deng Rangyu,Jiang Jiang,Zhang Chengyi.Research on High Performance General Purpose Microprocessor Architecture[J].Journal of Computer Research and Development,2006,43(6):987-992. |
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| Authors: | Zhang Minxuan Wang Yongwen Xing Zuocheng Deng Rangyu Jiang Jiang Zhang Chengyi |
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| Affiliation: | School of Computer Science, National University of Defense Technology, Changsha 410073 |
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| Abstract: | The X processor is an EPIC based high-performance general-purpose microprocessor. Eight-stage pipelines and OLSM execution model are designed, which overcomes the limitations of traditional EPIC execution model with little hardware overhead. A multi-branch predication structure is designed for parallel execution of multiple branch instructions. Predication is used to reduce branch instructions. Two-level cache memory is designed. DTD method is presented for low power design and speculation is used to hide memory latency. Finally, the future of high-performance microprocessors is prospected. |
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| Keywords: | microprocessor architecture parallelism branches memory |
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