A single poly EEPROM cell structure for use in standard CMOSprocesses |
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Authors: | Ohsaki K. Asamoto N. Takagaki S. |
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Affiliation: | Adv. Syst. Dev., IBM Japan Ltd., Shigaken; |
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Abstract: | A single poly EEPROM cell structure implemented in a standard CMOS Process is developed. It consists of adjacently placed NMOS and PMOS transistors with an electrically isolated common polysilicon gate. The common gate works as a “floating gate”. The inversion layer as “control node (gate)”. Test chips which were fabricated in a 0.8 μm/150 Å standard CMOS logic process showed 5-9 V of threshold voltage shift and more than 10000 cycles of endurance with good data retention under high temperature. This EEPROM cell can be easily integrated with CMOS digital and analog circuits |
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